1. Field of the Invention
The present invention relates to data processing and data storage, and more particularly to precompensation of write data signals.
2. Background Art
Computer systems employ data storage devices, for example, disk drives, to store data for use by the computer system. A typical data storage device includes storage media, in which data is stored, a read head, and a mechanism, such as a motor, for imparting relative motion between the storage media and the read head. The relative motion allows access to various portions of the storage media, and, in the case of certain types of media, such as magnetic media, allows for the production of signals representative of the data stored in the storage media.
In general, disk memories are characterized by the use of one or more magnetic media disks mounted on a spindle assembly and rotated at a high rate of speed. Each disk typically has two surfaces of magnetic media. In a typical rotating medium as a storage system, data is stored on magnetic or magneto-optical disks in a series of concentric xe2x80x9ctracks,xe2x80x9d with each track being an addressable area of the memory array. A read/write head is provided for each surface of each disk in the disk storage system. These tracks are accessed by read/write head that detects variations in the magnetic orientation of the disk surface.
To provide retrieval of stored data from a storage medium, the fixed representation of the stored data in the storage medium must be converted into signal that may be processed to yield data in a form usable with a system such as a computer system. A read channel circuit is used to convert signals from the storage media to usable read data.
Information is often provided to a read channel in a bit stream format. A bit stream consists of a series of logical ones or zeros presented in serial fashion. To accurately decode a serial bit stream, the read channel must be able to detect each individual bit. To isolate each bit, a bit frame or bit window is defined about each bit. A bit window should only contain a single bit. If the window is too large, more than one bit of information may be contained within the window and one or all bits may be lost. If the bit window is too small, no detectable information will result. Further, loss of bit information at point locations may lead to error propagation throughout the decoding process.
A read channel circuit is used to read data from a storage device, for example a hard disk drive. A read channel circuit typically includes a pulse detector, a filter, servo circuits, a data synchronizer, a window shift circuit, a write precompensation circuit, an encoder/decoder (ENDEC), and a control circuit. The pulse detector detects and qualifies encoded read signals derived from the storage device. The filter further processes the encoded read signals to ensure frequency range and phase relationships of the encoded read signals are appropriate to allow read data to be recovered from the encoded read signals. The servo circuits capture servo information derived from the storage device which is used to assure that data to be read from the storage device has been accurately located.
In the read mode, the data synchronizer performs sync field search and data synchronization. The data synchronizer uses a phase locked loop (PLL) to provide data synchronization and to develop a decode window. The window shift circuit shifts the phase of the voltage controlled oscillator (VCO) of the PLL to effectively shift the relative position of the read data pulse within the decode window. In the write mode, the write precompensation circuit uses the data synchronizer to provide data encoding and independent late/early write precompensation for NRZ data. The ENDEC provides encoding and decoding, preferably of run length limited (RLL) signals. The control circuit coordinates and controls the operation of the aforementioned circuits and subsystems.
A write precompensation circuit provides write precompensation. Write precompensation compensates for media bit shift caused by magnetic nonlinearities. Specific write data patterns are recognized and delays are added in the time position of write data bits to counteract the effects of the magnetic nonlinearities. The magnitude of the time shift required depends on the specific nonlinearities of the particular magnetic media involved. Therefore, the amount of precompensation is typically be made programmable to allow users the flexibility to set the amount needed in specific applications. Pre-compensation is performed only on the second of two consecutive xe2x80x9conesxe2x80x9d in a write data stream and shifts the time position of the write data bits in only the late direction. If more than two consecutive xe2x80x9conesxe2x80x9d are written in a write data stream, all but the first are precompensated in the late direction.
FIG. 1 is a schematic diagram illustrating a typical write precompensation circuit.
Circuit 101 is a portion of the circuit of FIG. 1. Circuit 101 comprises transistors 106, 107, 111, 113, 114, 117, 118, 121, 122, 123, 124, 128, 129, 133, 134, 137, 138, 139, 140, 146 and 147. Circuit 101 comprises resistors 108, 109, 112, 119, 120, 125, 126, 127, 131, 132, 136, 141, 142 and 148. Circuit 101 comprises capacitor 115, current source 130 and variable current source 149.
The circuit of FIG. 1 comprises timing generator 102 and comparator 103. Timing generator 102 comprises transistors 106, 107, 111, 113, 114, 117 and 118. Timing generator 102 comprises resistors 108, 109, 112, 119 and 120. Timing circuit 102 comprises capacitor 115. Comparator 103 comprises transistors 133, 134, 135, 137, 138, 139, 140, 146 and 147. Comparator 103 comprises resistors 131, 132, 136, 141, 142 and 148. Comparator 103 comprises variable current source 149.
Input CLK at node 104 is coupled to the base of transistor 106 and to the base of transistor 129. Input CLK* at node 105 is coupled to the base of transistor 107 and to the base of transistor 128. Positive voltage supply V+ at node 150 is coupled to a first terminal of resistor 108 and to a first terminal of resistor 109. A second terminal of resistor 108 is coupled to node 152, at which signal Vno is present, to the collector of transistor 106 and to the base of transistor 114. A second terminal of resistor 109 is coupled to node 153, at which signal Vpo is present, to the collector of transistor 107 and to the base of transistor 113.
Input Vbias at node 110 is coupled to the base of transistor 111, to the base of transistor 123, to the base of transistor 124, to the base of transistor 135, to the base of transistor 139 and to the base of transistor 140. The emitter of transistor 111 is coupled to a first terminal of resistor 112. The second terminal of resistor 112 is coupled to ground at node 151. The collector of transistor 111 is coupled to the emitter of transistor 106 and to the emitter of transistor 107.
Positive voltage supply V+ at node 150 is coupled to the collector of transistor 113 and to the collector of transistor 114. The emitter of transistor 113 is coupled to the base of transistor 122, to a first terminal of capacitor 115, to the collector of transistor 117, and to node 154, at which signal Vcp is present. The emitter of transistor 114 is coupled to the base of transistor 121, to the second terminal of capacitor 115, to the collector of transistor 118, and to node 155, at which signal Vcn is present.
Voltage Vc is measured across capacitor 115, with node 154 being the positive terminal and node 155 being the negative terminal for the purposes of measurement. The emitter of transistor 117 is coupled to a first terminal of resistor 119. The second terminal of resistor 119 is coupled to ground at node 151. The emitter of transistor 118 is coupled to a first terminal of resistor 120. The second terminal of resistor 120 is coupled to ground at node 151. Input VADJ at node 116 is coupled to the base of transistor 117 and to the base of transistor 118.
Positive voltage supply V+ at node 150 is coupled to the collector of transistor 121 and to the collector of transistor 122. The emitter 121 is coupled to the collector 123, to the collector of transistor 128, and to a first terminal of resistor 127. The emitter of transistor 122 is coupled to the collector of transistor 124, to the collector of transistor 146, and to a first terminal of resistor 148. The emitter of transistor 123 is coupled to a first terminal of resistor 125. The emitter of transistor 124 is coupled to a first terminal 126. The second terminal of resistor 125 and the second terminal of resistor 126 are coupled to ground at node 151. The emitter of transistor 128 and the emitter of transistor 129 are coupled to a first terminal of current source 130. The second terminal of current source 130 is coupled to ground at node 151.
Current IE is measured through current source 130. The second terminal of resistor 127 is coupled to the collector of transistor 129, to the base of transistor 133 and to node 156, at which signal Vin is present. The second terminal of resistor 148 is coupled to the base of transistor 134, to the collector of transistor 147, and to node 157, at which signal Vip is present.
Positive supply voltage V+ at node 150 is coupled to a first terminal of resistor 131 and to a first terminal of resistor 132. A second terminal of resistor 131 is coupled to the collector of transistor 133 and to the base of transistor 137. The second terminal of resistor 132 is coupled to the collector of transistor 134 and to the base of transistor 138. The emitter of transistor 133 and the emitter of transistor 134 are coupled to the collector of transistor 135. The emitter of transistor 135 is coupled to a first terminal of resistor 136. The second terminal of resistor 136 is coupled to ground at node 151.
Positive supply voltage V+ at node 150 is coupled to the collector of transistor 137 and to the collector of transistor 138. The emitter of transistor 137 is coupled to a negative side of a second input of AND gate 143, to a positive side of a first input AND gate 144, to the collector of transistor 139 and to node 166, at which signal 01 is present. The emitter of transistor 138 is coupled to a positive side of a second input of AND gate 143, to a negative side of a first input of AND gate 144, to the collector of transistor 140, and to node 167, at which signal O1* is present.
The emitter of transistor 139 is coupled to a first terminal of resistor 141. The emitter of transistor 140 is coupled to a first terminal of resistor 142. The second terminal of resistor 141 and the second terminal of resistor 142 are coupled to ground at node 151. Input WPL at node 158 is coupled to a noninverting side of a first input of AND gate 143. Input WPL* at node 159 is coupled to a inverting input of AND gate 143.
The noninverting output of AND gate 143 at node 168 provides output OL and is coupled to the base of transistor 147. The inverting output of AND gate 143 at node 169 provides output OL* and is coupled to the base of transistor 146. The emitter of transistor 146 and the emitter of transistor 147 are coupled to the output of digital-to-analog converter (DAC) 801 of variable current source 149 at node 809. Current IL is measured through node 809.
Input WDT is at node 160 is coupled to a noninverting side of a second input of AND gate 144. Input WDT* at node 161 is coupled to an inverting side of a second input of AND gate 144.
The noninverting output of AND gate 144 provides signal WPT at node 162 and is coupled to an noninverting input flip-flop 145. The inverting output of AND gate 144 provides signal WPT* at node 163 and is coupled to an inverting input of flip-flop 145. The noninverting output of flip-flop 145 provides output WDout at node 164. The inverting output flip-flop 145 provides output WDout* at node 165.
The emitter of transistor 146 and the emitter of transistor 147 are coupled to node 809, which is coupled to the current output of DAC 801. The current reference input of DAC 801 is coupled to a first terminal of current source 802 at node 808. A second terminal of current source 802 is coupled to ground 806 at node 807.
DAC 801 has a digital input 803 for receiving digital information. The digital information at digital input 803 may be provided to any suitable digital control means, for example a microcontroller, coupled to digital input 803. Digital input 803 may be a digital input comprising one or more nodes, with each node conveying at least one bit of digital information. For example, digital input 803 may include node 804, which conveys the most significant bit (MSB) of digital information, and node 805, which conveys the least significant bit (LSB) of digital information.
DAC 801 receives a reference current input from current source 802 and digital information from digital input 803. DAC 801 provides a current output at node 809 that is a function of the current at the reference current input and the digital information at digital input 803. Thus, by varying the digital information at digital input 803 while maintaining a constant reference current at the reference current input at node 808, the circuit comprising DAC 801 functions as a variable current source.
FIG. 1 shows a typical circuit used in realizing write precompensation. The magnitude of the precompensation is made proportional to the time base generator""s VCO period which sets the basic write rate by duplicating a portion of time base generator""s VCO as shown in timing generator 102 of FIG. 1.
FIG. 2 is a timing diagram illustrating waveforms and timing relationships of the signals of the circuit of FIG. 1.
FIG. 2 shows waveforms at several internal nodes. Comparator 101 of FIG. 1 compares Vip and Vin, both of which are offset from Vcp and Vcn by IL*RL and IE*RE respectively. On the rising edge of clock signal CLK at node 104, the early side, signal Vin at node 156, is set via transistors 128 and 129 and the late side, signal Vip at node 157, is set (reset) if the previous bit signal WPL was 1(0) via transistors 146 and 147 and AND gate 143. As signal Vin at node 156 ramps down, the condition of Vip greater than Vin is reached and the comparator fires or resets and generates a positive going transition which is passed through AND gate 144 and causes flip-flop 145 to toggle. By varying the current IL through variable current source 149, the trip point is changed and the desired time delay is generated. AND gate 144 prevents the transition from passing through unless the data WDT is valid (i.e., xe2x80x9c1xe2x80x9d). AND gate 143 keeps signal Vip at node 134 reset unless previous data bit signal WPL is a logical xe2x80x9c1xe2x80x9d. Again note that the first data bit is not precompensated or delayed.
On the falling edge of the clock signal CLK at node 104, with the late side already reset by the regenerative action of the comparator via AND gate 143 and transistors 146 and 147, the early side is reset and the late side begins to ramp down. When Vin greater than Vip, the comparator is set again, aided by the regenerative action via AND gate 143 and transistors 146 and 147 and awaits the next data bit.
When a larger amount of write precompensation is desired, signal Vip at node 157 is set lower to delay the occurrence of the trip condition Vip greater than Vin. Under extreme conditions when Vip is set too low, the comparator may fail to fire and a transition may be completely missed. This is a catastrophic failure and, as such, must be avoided. Also note that the range of the precompensation is limited by the duty cycle of the basic clock to less than 50% even under ideal conditions and to much less (typically about 30%) in a real environment.
In the past, catastrophic failure has been avoided by limiting the precompensation range to a fairly small range, such as 20%, thereby allowing adequate margin for clock jitter and/or noise.
The present invention provides a method and apparatus for preventing catastrophic failure (i.e., failsafing) and extending the range of a write precompensation circuit.
The present invention prevents such catastrophic failures from occurring without limiting the precompensation range to a small value and also extends the range of precompensation beyond limits imposed by the duty cycle of clock signal CLK. In some applications, particularly at high data rates, the amount of precompensation needed might be greater than 30%. Thus, the present invention provides advantages over the prior art.
The present invention prevents catastrophic failure of a write precompensation circuit by ORing either the input (signals Vip and Vin) or the output (signals O1 and O1*) of the comparator and the opposite phase of complementary clock signals CLK and CLK*. The opposite phase of the clock signals may be obtained by interchanging (i.e., swapping) the complementary clock signals with each other.
By ORing the input or output of the comparator with the opposite phase of the clock signals, a transition is guaranteed. If the comparator fails to generate a transition due to noise or clock jitter, the 180 degree delayed clock will force a transition.
In the preferred embodiment of the present invention, elements are included to prevent narrow pulses from interfering with proper operation of the write precompensation circuit, thereby making the write precompensation circuit less susceptible to noise and jitter.
The present invention extends the range of precompensation that a write precompensation circuit is able to provide. The clock signal and the clock signal that has been delayed by a time td are ORed together to change the duty cycle of the clock signal. By ORing together the clock signal and the delayed clock signal, the present invention provides a new clock signal having a greater duty cycle. The greater duty cycle allows a write precompensation circuit according to the present invention to provide longer precompensation delay. The preferred embodiment of the present invention also provides for a correction current to be inserted in the delay circuit to maintain constant duty cycle over a broad range of data rates.
Thus, the present invention overcomes the disadvantages of the prior art.